1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device using a Chemical Mechanical Polishing (CMP) process for surface planarization.
2. Description of the Prior Art
In recent years, surface planarization techniques have been becoming very important to form multilevel wiring or interconnection structures in Large-Scale Integrated (LSI) circuits.
In the multilevel wiring structures, electrical interconnection between different-level wiring layers is achieved by using electrically conductive plugs that are formed in contact holes of an interlayer dielectric layer intervening between the wiring layers. The conductive plugs are typically made of a metal such as tungsten (W).
Conventionally, the metallic conductive plugs are typically formed in the following way.
First, contact holes are formed in an interlayer dielectric layer to penetrate the same. Then, a metallic material is deposited on the interlayer dielectric layer by a Chemical Vapor Deposition (CVD) process having a good gap-filling capability. The metallic material is deposited not only on the surface of the interlayer dielectric layer but also on the bottom and side walls of the contact holes during this process.
Subsequently, the deposited metallic material on the surface of the interlayer dielectric layer is subjected to a CMP process until the surface of the interlayer dielectric layer is exposed, thereby removing the deposited metallic material on the surface of the interlayer dielectric layer while leaving the deposited metallic material in the contact holes. Thus, the surface of the interlayer dielectric layer is exposed and planarized and at the same time, the contact holes are filled with the metallic material. The remaining metallic material in the contact holes serves as the conductive plugs.
Since the surface of the interlayer dielectric layer including the tops of the conductive plugs is planarized, there is an advantage that a metallic layer for a next wiring layer can be formed on the planar surface.
The CMP process has the following advantages. First, the chip-level planarity, which is required for giving a specific margin to the depth of focus in photolithography, is realized. Second, the fabrication yield and reliability are improved because the required metallic plugs are surely formed and the probability of open circuit is decreased.
Therefore, the CMP process has been applied not only to the planarization of surface steps (i.e., hills and valleys), and the formation of trench isolation structures, trench capacitors, contact plugs, and damascene wiring structures.
In the CMP process, typically, a semiconductor wafer or substrate is held on a rotating carrier and a polishing pad is attached onto a rotating table. The pad is then contacted with the surface of a target layer on or over the wafer while supplying a slurry as a polishing medium to the contact area of the target layer with the pad. The slurry is typically made of a solution of a strong alkali or acid in which colloidal silica or alumina particles are dispersed. The surface of the target layer is chemically polished by the strong alkali or acid and at the same time, mechanically polished by the silica or alumina particles.
FIG. 1 shows a partial cross-section of a semiconductor device with a multilayer wiring structure.
As shown in FIG. 1, the semiconductor device 1440 is comprised of a semiconductor (e.g., single-crystal silicon) substrate 1400, a first interlayer dielectric layer 1422 formed on a surface of the substrate 1400, a first-level wiring layer 1401 formed on the first interlayer dielectric layer 1422, a second interlayer dielectric layer 1402 formed on the first-level wiring layer 1401, a second-level wiring layer 1407 formed on the second interlayer dielectric layer 1402, and a third interlayer dielectric layer 1432 formed on the second-level wiring layer 1407.
The layered structure including wiring layers in a third level or higher, which are located above the third interlayer dielectric layer 1432, is omitted here for the sake of simplification.
The substrate 1400 has a diffusion region 1400a in its surface area.
The first- and second-level wiring layers 1401 and 1407 have specific wiring patterns.
The first interlayer dielectric layer 1422 has a contact hole 1423 filled with a metallic barrier layer 1424 and a metallic plug 1425a. The barrier layer 1424 covers the bottom and side walls of the contact hole 1423. The metallic plug 1425a is located on the barrier layer 1424. The diffusion region 1400a and the first wiring layer 1401 are electrically connected to one another through the metallic plug 1425a and the barrier layer 1424.
Similarly, the second interlayer dielectric layer 1402 has a contact hole 1403 filled with a metallic barrier layer 1404 and a metallic plug 1405a. The barrier layer 1404 covers the bottom and side walls of the contact hole 1403. The metallic plug 1405a is located on the barrier layer 1404. The first wiring layer 1401 and the second first wiring layer 1407 are electrically connected to one another through the metallic plug 1405a and the barrier layer 1404.
With the semiconductor device 1440 shown in FIG. 1, the barrier layer 1404 and the metallic plug 1405a are, for example, formed in the contact hole 1403 of the second interlayer dielectric layer 1402 in the following way.
As shown in FIG. 2A, after the second interlayer dielectric layer 1402 is formed on the first-level wiring layer 1401, the contact hole 1403 is formed in the layer 1402 by known processes. Then, the barrier layer 1404 is formed on the second interlayer dielectric layer 1402 to cover the contact hole 1403 by a known process. The barrier layer 1404 covers not only the surface of the second interlayer dielectric layer 1402 but also the bottom and side walls of the contact hole 1403.
Subsequently, a metallic layer 1405, which is typically made of tungsten, is formed on the barrier layer 1404 by a CVD process. In this process, as clearly shown in FIG. 2A, the surface of the metallic layer 1405 becomes very rough, because the metallic layer 1405 has different growth rates according to the crystal-growth directions. Consequently, the contact hole 1403 is not fully filled with the metallic layer 1405, resulting in a narrow gap 1403a termed a void at the contact hole 1403.
Then, the metallic layer 1405 and the barrier layer 1404 are removed until the surface of the second interlayer dielectric layer 1402 is exposed by a CMP process, thereby forming the contact plug 1405a in the contact hole 1403. During this CMP process, the gap or void 1403a is left in the plug 1405a. Because the top of the gap or void 1403a is opened due to the polishing action, the gap 1403a is fully filled with a polishing residue 1406, as shown in FIG. 2B.
The polishing residue 1406 filled in the gap 1403a is unable to be removed by a subsequent washing or cleaning process. Therefore, the polishing residue 1406 is left in the gap 1403a even after a washing or cleaning process.
Further, the second-level wiring layer 1407 is formed on the exposed and planarized surface of the second interlayer dielectric layer 1402 by a known process. Thus, as shown in FIG. 2C. the polishing residue 1406 is completely confined in the gap 1403a.
It has been found that the polishing residue 1406 in the gap 1403a serves as a contamination source to electronic devices on the substrate 1400, resulting in degradation of the performance and characteristics of the devices.
For example, the contact area between the contact plug 1405a and the second-level wiring layer 1407 is decreased and the contact resistance therebetween is increased. This leads to contact failure and/or abnormal operation. Also, it the polishing residue 1406 confined in the gap 1403a is released during a subsequent process, the residue 1406 will give bad effects to other devices, layers, or substrates.